1. Field on the Invention
The present invention relates to the field of the electronics, and particularly it relates to random access memory devices provided with error correction capabilities.
2. Discussion of the Related Art
A Random Access Memory (RAM) is a particular type of electronic memory wherein each memory address can be directly accessed with a same access time. A RAM memory includes an array of memory cells, each one of which is capable of storing a binary information or a bit (that is the logical value “0” or “1”), and corresponding peripheral circuits, which in general accomplish management and access functions to each memory cell.
Static RAM memory (SRAM) is a type of volatile RAM memory that does not require any operation for the refresh of the stored data, since the information is stored for a theoretically infinite time (until the shutdown of the electronic system in which such memory is implemented); SRAM memories have reduced access times and relatively low power consumption, especially in static conditions.
Conversely, dynamic RAM memory (DRAM) is a type of volatile RAM memory wherein each bit of data is stored in a separate capacitor. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Compared to SRAM, a DRAM has longer access times, but allows to reach higher densities.
In a SRAM memory, each single access involves a plurality of memory cells at the same time. Specifically, during a writing access, a data word formed by a plurality of bits is written into a corresponding group of addressed memory cells. This group includes a number of memory cells equal to the number of bits forming the word to be written; in this way, each bit of the data word is written into a corresponding memory cell of the group. Similarly, during a reading access, an addressed group of memory cells is accessed so as to read a corresponding data word from the memory cells thereof.
SRAM memory devices can be subjected to so-called “soft error” events, i.e., occurrences of unplanned inversions of the logical values stored in the memory cells caused by alpha particles, cosmic rays, thermal neutrons and random electrical noise. Errors due to such events can be solved through soft error correction techniques using proper Error Correction Codes (ECC). Specifically, each word stored in the SRAM memory is associated with corresponding matching redundant data, forming a respective “ECC word”. The ECC word is generated by an encoder/decoder unit from the value of the corresponding stored word by using a proper algorithm. As it is well known to those skilled in the art, using the ECC word, it is possible to detect and automatically correct possible unplanned data word variations caused by soft error events. The ECC words are typically stored in memory cells of the array; for this purpose, a portion of the array of memory cells may be specifically dedicated to store the various ECC words. For example, each row of the array of memory cells may be subdivided in two portions, and specifically a first portion (data portion) including the memory cells adapted to store a data word, and a second portion (ECC portion) including the memory cells adapted to store the corresponding ECC word. Every time a new data word is stored in the data portion of a row, or every time an already stored data word is modified during a writing access, the corresponding ECC word is accordingly updated.
In order to assist the carrying out of debugging operations during the test of the SRAM memory, each data word of the array is associated with auxiliary data, in jargon referred to as “applicative bits”. These applicative bits may be used by the debugger in different ways, for example in order to set customizable breakpoints adapted to interrupt the debugging procedure once a certain data word is reached.
According to a first solution known in the art, the applicative bits are stored in a dedicated SRAM memory array, distinct from the one wherein the data words (and the ECC words as well) are stored. However, this solution is very expensive in terms of costs, since it requires the use of two different memory arrays; moreover, in this case additional means (e.g., a lookup table) are required to establish relationships between each data word stored in the first array and the corresponding applicative bits stored in the second array.
According to a further solution known in the art, the applicative bits are stored in dedicated memory cells of the same array wherein the data words and the ECC words are stored. For example, each row of the array of memory cells may be subdivided in three portions, and specifically a first portion (data portion) including memory cells adapted to store the data word, a second portion (ECC portion) including the memory cells adapted to store the corresponding ECC word, and a third portion (applicative portion) including memory cells adapted to store the corresponding applicative bits. However, since the encoder/decoder unit typically generates each ECC word to be stored in the ECC portion of the corresponding row starting from the data stored in the remaining memory cells of the row, the resulting ECC word depends both on the data word (stored in the data portion) and on the applicative bits (stored in the applicative portion). This is disadvantageous, since the ECC words should not be influenced by any application bits modification; in this case, indeed, in order to modify the application bits stored in the applicative portion, the data word stored in the data portion would be previously read, and then, after the modification of the applicative bits, the ECC would be recalculated taking into account both the new application bits and the previously read data word.
Therefore, the Applicant has found that currently known SRAM devices provided with error correction capabilities may be neither cost-effective nor efficient. Generally speaking, the Applicant has found that none of the presently known SRAM devices fulfill at the same time all the following requirements:                allowing to access the applicative bits independently from the data bits;        having the applicative bits and the data bits that can be accessed (both in reading and in writing) with a same access time, and        having a reduced area occupation within the semiconductor chip wherein the memory device is integrated.        